Variance FX™ is the first and only practical solution for variation characterization of custom logic blocks and macros. It is currently in production at the most advanced FinFET process nodes available in the market today. Based on CLKDA’s FX model (see http://www.clkda.com/the-fx-model-simulator/), Variance FX™ generates variation models for complex Macros in seconds per arc.  Because the FX simulator does not use any sampling, and solves for variation mathematically, it is both 1000’s of times faster than MC SPICE and more complete. In addition, Variance FX™ identifies the minimum circuit per arc, and thereby reduces the total simulation time 100’s of times more. 

Custom Logic Macros, FinFETs & Variation Modeling

One of the more interesting developments in FinFET SoC design is the return of custom logic and ‘macros’. These large functional blocks include large bit count register trays, pulse latches, retention flops, and programmatic delay buffers. In FinFETs, they can play an essential role in optimizing power, performance and area. 

Implementation of custom logic in FinFETs requires new characterization methods, especially for modeling process variation. Just like standard logic cells, custom cells are subject to all of the same process variation effects that are inherent in small geometries.  Process variation, particularly at lower voltage operation, can have a 2x impact on delay that has to be captured for static timing analysis. Because these are much larger blocks, Monte Carlo SPICE is prohibitively expensive to run (remember SPICE and Fast SPICE run times increase dramatically with the number of nodes). 

Variance FX is specifically designed for variance characterization of complex custom logic blocks. It can generate both AOCV derates, as well as full Liberty Variation Format tables 1000’s of times faster than any SPICE and sample based solution. 

Variance FX begins with the foundry SPICE model, the Liberty model and the extracted layout netlist (LPE) for each macro. Macro FX reads in the netlist, creates FX models for each of the transistors, and identifies the functional structures within the macro. Using this information, Variance FX™ determines the possible arcs through the macro. If the Liberty file defines specific “when” conditions or set-ups for the arcs, it will use that as additional guidance in arc determination.  Once Variance FX has traced all possible arcs, it then characterizes each of the arcs for variation and creates a variation database. From the variation database, Variance FX can generate AOCV, LVF, POCV, SOCV tables or Liberty files for the macro. 

Variance FX is orders of magnitude faster than MC SPICE. For an 8 bit register, Variance FX can evaluate one load/slew/arc point for variance in 110 seconds. MC SPICE requires 1045 seconds per sample. Using 500 samples, this equals 522,500 seconds or 6 days!