The FX Application Suite is improving SoC yield, performance, and time-to-market for the most challenging designs in the market today.  The FX Application Suite is the only solution that combines the accuracy and performance needed to eliminate timing sign-off errors and increase confidence that first silicon will meet specification.  

The FX Application Suite finds the problems other tools can’t. It delivers MC SPICE accurate answers for delay and variance (process, temperature and voltage) at the cell, path, clock, and chip level thousands of times faster than any SPICE or Fast SPICE based solution. Each application solves specific problems with MC SPICE accuracy - AOCV/POCV/SOCV/LVF table generation, critical path analysis, clock tree analysis – and complements existing tools – STA, cell characterization, physical optimization. FX is a trusted circuit model, and is in production at 40nm, 28nm, 20nm, 16nm, 14nm and 10nm. FX has been validated at all of the major foundries, with multiple libraries, both third party and proprietary.

Every Picosecond Counts below 28nm – There is no room for error, guesses or over-margining

Leading edge designs take even the most advanced silicon processes to their limit. They require high clock speed and low power consumption, across extreme operating ranges – from over clocking to ultra-low voltage at 0.5V. And these designs are targeted at highly competitive markets, where a three-month delay can mean failure. Yet cell delays can swing by 2x between low and high voltage corners, and process variance can be 50% or more of total path delay in one timing corner alone. Traditional Static Timing Tools can miscalculate delay by 20% or more on high fan-out paths on top of only being ±5% of SPICE on average.

Here is the designer’s dilemma. When every picosecond counts, there is no spare margin to over guardband the design. Adding extra delay pads or clock uncertainty makes it impossible to close timing at 100+ corners. However, traditional STA tools using CCS models and OCV adjustments are not accurate enough to sign-off without over-margining.  Sign-off right to the edge of the corners will be fatal, but no one can afford to wait for first silicon to find out the real frequency and power consumption is.

The FX Application Suite: Accuracy and Performance Without Compromise

The FX Application Suite is uniquely designed to eliminate the error and the guesses. Each of the FX applications addresses a critical part of getting to sign-off with higher confidence that timing results correlate  to first silicon: the real clock frequency, the worst negative slack and total negative slack of a design with process variance at each of the sign-off corners, eliminating hidden hold violations… Each of the applications solves a specific problem to Monte Carlo SPICE accuracy, orders of magnitude faster than any other solution: what is the delay on these critical paths with process variance across voltages, what is the AOCV/SOCV/LVF derate or sigma for every arc/load/slew on every cell in this library, what is the insertion delay and skew at every node on all of the clocks in this design?