Path FX™ delivers Monte Carlo SPICE accurate timing with the ease of use and performance of a general purpose, static timing analyzer. Path FX can run 10’s of thousands of paths in minutes with MC SPICE accuracy. Path FX is a complete path based static timing analyzer that complements existing sign-off flows. Traditional CCS based static timing analyzers can be off by 20% or more. Path FX is within 2% of SPICE, by using transistor level timing, and correctly modeling Miller Capacitance, waveform propagation, local voltage, multi-voltage paths and simultaneous switching. Path FX is used for multiple applications: critical path sign-off, timing methodology calibration, multi-voltage path analysis for voltage domain crossings, and critical path voltage sensitivity (shmoo analysis).
Path FX’s performance and accuracy are made possible by FX. FX is a trusted transistor model, circuit simulator and variance solver that is at the heart of CLKDA’s margin analysis applications. FX has been validated at all of the major foundries, at 28nm, 20nm, 16nm and 14nm, on all of the major models (BSIM4, BSIMSOI, PSP, BSIMCMG, etc.), and on multiple proprietary and all third party libraries. It is currently in production at the most advanced process nodes in use today. The FX Variance Platform provides 3σ statistical accuracy 300,000 to 500,000 times faster than Monte Carlo SPICE.
Today’s Advanced SoC’s require SPICE accurate timing
Today’s advanced SoC’s require a new approach to timing. Teams must deliver silicon to an aggressive specification and target yield. Existing STA tools are at best ±5% of SPICE for basic delay under the best of conditions. Under the worst of conditions, with process variance, low voltage operation and complex circuits, they can be wrong by as much as 20% or more. This inaccuracy forces design teams to add margin and guardbands. But over-guardbanding and adding unnecessary margin to protect against fatal hold violations can make it impossible to tape-out on schedule at the target power and speed. Having actual frequency run 20% or 30% higher than STA predicted has no value, and usually comes at the expense of power.
Traditional STA can be wrong by 20% or more
Traditional Static Timing Analyzers can be wrong by 20% or more. The first source of error is inaccurate delay calculation. STA tools depend on simplified delay models that mask the real circuit behavior. Simultaneous switching, multiple input switching and Miller capacitance are either ignored, or estimated during cell characterization. These base delay errors can be as much as 5% or more. The second effect is impact of process variance. Process variance can cause delay to shift as much as 50% on an individual cell and can add another 5% to 10% on path delay. Third, when low voltage operation and local voltage variation, are taken into account the total error can grow to as much as 20% or more.
Though these effects may cancel out on many paths, on some paths they will accumulate, and become critical. Timing is about finding the exceptions, not the average.
Delay Calculation Errors in Traditional STA
Traditional STA tools simplify or ignore many critical circuit effects. Because STA depends on pre-characterized Liberty cell models, such as NLDM, or CCS, many critical circuit effects cannot be captured. Waveforms do not propagate through cells (they are converted back to simple linear ramps), only one input is switching at a time vs. multiple input switching, (cell characterization only evaluates one input at a time), side inputs are fixed, and receivers are treated as simple pins capacitance loads.
The graphic below illustrates the impact of one of these effects, Miller capacitance. At 20nm and below, the Miller effect can be the dominant capacitive load on nets with multiple receivers. In traditional STA tools, the receivers on a path are treated as a ‘dead’ load or simple pin capacitance. In fact, a receiver is an ‘active’ load. This is because of the Miller effect, wherein there is a feedback effect such that the capacitive loading effect changes as the receiver is driven. As the graph illustrates, the delay can shift out by as much as 5%, or even more at lower voltage operation.
Process Variance Impact on Delay
At small geometries, process variance can cause a 50% or more swing in delay. The graphic to the right shows the sensitivity of delay of a 28nm inverter to path depth. On shallow critical paths (which are very typical on the hold side), process variance contributes a major portion of the total delay.
Correct accounting for process variance means that static timing delays must be adjusted in every dimension. Delay, slew and the timing constraints themselves have to include the impact of process variance.
Voltage Variation & Voltage Operation
Local voltage variation or IR drop, can have a major impact on delay. That is why there are specialized tools that analyze voltage variation for at risk locations. Yet there is no way to put voltage information into the STA tools, other than large voltage offsets that penalize all nets.
The adoption of ultra-low voltage operation for power conservation puts even more stress on timing. Low voltage operation dramatically increases the impact of process variation. Not only is delay much more sensitive to process variation, but the sensitivity is non-Gaussian. When a distribution is non-Gaussian (non-normal), the variance is skewed, and has a much higher impact.
The figures to the right illustrate the sensitivity of delay of a 20nm inverter from 1V to .6V, and the skewed or non-Gaussian distribution at 1 and .65V. The voltage sweep shows how wide a swing process variance can cause. The distribution graph shows the asymmetric/non-Gaussian nature of variance at ultra-low voltage. The result is that delay can be dramatically shifted out past the expected values. Again, there is no way to accurately capture this impact in today’s STA tools.
Path FX: Production Proven Performance, Accuracy, Functionality
Path FX has made SPICE accurate critical path analysis a reality. It has the performance to evaluate 10’s of 1000’s of paths per hour for delay and variance; production proven accuracy on the most advanced manufacturing processes; and the functionality to account for all critical timing effects.
Performance: Path FX is literally like running SPICE on all of the critical paths for delay and variance, but in an STA environment with STA throughput. Path FX is a fully distributed application that can use hundreds of processors in a network. With 100 processor threads, Path FX can evaluate 1 million+ paths per hour per corner for delay and 100’s of thousands of paths for variance.
Production Proven Accuracy: FX has been proven in production on more designs and libraries than any other commercial solution in the market today. FX has been validated at all of the major foundries, at 28nm, 20nm, 16nm and 14nm, on all of the major models (BSIM4, BSIMSOI, PSP, BSIMCMG, etc.), and on multiple proprietary and all major third party libraries. It is currently in production at the most advanced process nodes on some of the leading SoC designs. FX results are typically within 2% of the leading commercial SPICE solutions.
Complete critical path timing environment from data input to reports: Path FX is a complete static timing solution for critical path analysis. It reads standard data input formats (Verilog, SDC, SPEF, Liberty), and produces easy to read timing reports.
Easy integration into PrimeTime and PrimeTime SI: Path FX reads a list of critical paths from PrimeTime or PrimeTime SI. The PrimeTime SI crosstalk push out can also be included in delay calculations.
Calculates Corner or Statistical Timing: Path FX can calculate SPICE accurate timing from traditional sign-off corners (including AOCV or LVF), or statistically from global corners. Path FX has the option to calculate timing constraints on a path instance basis for precise slack measurement.
True Transistor Level Timing Captures True Circuit Timing: FX is a transistor level model. This enables Path FX to inherently capture the real circuit level behavior. Waveforms are properly propagated through the gates, and receivers are treated as active loads (Miller effect). Users can set multiple input switching conditions, or determine side input conditions to capture more complex effects.
Multi-Voltage Path Support: Because FX is a transistor level model, Path FX handles multi-voltage paths automatically. Waveforms are correctly propagated through level shifters, and all voltages are properly resolved.
Voltage Sweeping and Multi-Corner Analysis: Path FX also has the capabilities to perform multi-voltage path sweeps (aka Shmoo plots), and multi-mode, multi-corner analysis. Once a design has been read in, along with a list of critical paths, it is very easy to then evaluate those paths across multiple scenarios.
SDF Generation: Path FX supports the export of SDF files (standard delay format), which can be used to direct final sign-off timing or physical design optimization.
Easy Integration with Your STA and PD Flow
Path FX complements your existing sign-off and physical design flows. The inputs for the FX models are your libraries and foundry SPICE models. The inputs for Path FX are the design files (Verilog, SPEF, SDC), and a list of critical paths from your STA tool such as PrimeTime or PrimeTime SI. The outputs are timing reports, black box models, or SDF timing data that can be input back into your optimization tools or static timer.
Path FX: SPICE Accurate Timing Made Practical
Path FX has made SPICE accurate timing both possible and practical for SoC designs. It is fast, production proven at the most advanced process nodes, and functionally robust. It complements existing sign-off and physical design flows to materially improve chip frequency, yield and time to market.