When chip designers talk about volume production -- whether it's timing sign-off, timing derates, analyzing clocks, characterizing libraries for delay/voltage/variance, predicted power, voltage schemes, or predicted yield, their Biggest 3 top collective goals are always: 1. more margin 2. more margin 3. more margin. Margin is the heart of physical design flows. And a chip's margin ownership is usually spread between four groups: - the physical design team - the library and characterization team - the foundry's process interface team - the foundry itself Each of these groups are caught up in a perpetual tug-of-war against each other over margin. During sign-off, they each use margin to pad against surprises in timing, clocks, power grids, yield, manufacturing variance, and even in the manufacturing delivery time table itself. This means margining convergence is a negotiated practice. In most cases, to be competitive the chip design team must be granted foundry waiver(s). Generally larger volume customers pay for good die and not wafers. Thus it's the foundry's best interest to have the tightest distribution for yield available. Thus revenue-per-wafer increases and the foundry makes money. The waivers are granted at the risk of the design company. Depending on how much margin the design company and the foundry each get, pretty much decides who'll get the most money from the chip deal.