Path FX™ has specialized functionality for clock tree analysis. It is equivalent to running Monte Carlo SPICE on every clock tree on an SoC, but 400,000x faster, and using the same flow as a static timing analyzer.  Path FX can evaluate every clock tree in a 100 million instance, design in under three hours, with full SPICE accuracy. Path FX is a complete clock analysis solution that complements existing physical design and timing flows. Path FX identifies the clock trees, analyzes them to within 2% of SPICE for insertion delay, skew and variance, and then generates both clock-by-clock reports, and SDF files for back annotation into other tools.  

Clock Trees are at the Heart of Design Frequency

Clock Trees determine design frequency. But with today’s multi-voltage, multi-clock designs getting more and more complex, early iterations in the design flow rely on heavy guardbanding of the clock to protect against hold violations, and to force the physical design optimization to over perform on frequency. Additional insertion delay, clock uncertainty, and OCV factors are added in to pad the clock.

But what is the real design frequency?

Sign-off deadlines, and thousands of remaining timing violations force designers to look for slack. But existing STA tools are at best ±5% of SPICE for basic delay. Under the worst of conditions, with process variance, low voltage operation and complex circuits, they can be as much as 20% off. They cannot be trusted to accurately and safely calculate clock insertion delay and skew.

No one can wait for first silicon to find out the actual frequency and yield.  Having actual frequency run 20% or 30% higher than STA predicted has no value, and usually comes at the expense of power.

Traditional STA Clock Timing is Inaccurate; SPICE is too slow

STA can be wrong by 20% or more. The first source of error is delay calculation. STA tools use simplified delay models that mask the real circuit behavior. Effects like simultaneous switching, multiple input switching and active receivers, are either ignored, or estimated during cell characterization. These base delay errors can be as much as 5% or more. The second effect is impact of process variance. Process variance can cause delay to shift as much as 50% on an individual cell and can add another 5% to 10% error on clock delay.    Third, when low voltage operation and local voltage variation, are taken into account the total error can grow to as much as 20% or more.  Given this level of error, the traditional solution has been guardbands – which mask real timing and make sign-off nearly impossible.

SPICE, however, is much too slow.  Simulating one tree can literally take days per corner, not to mention all of the complications to set the circuit up correctly first.

Path FX: Production Proven Accuracy, Performance and Functionality

Path FX has made SPICE accurate clock tree analysis a reality. It has the performance evaluate all of the clock trees in an SoC for delay and variance; production proven accuracy to tackle the most advanced manufacturing processes; and the functionality to account for all critical contributors across multiple PVT corners and scenarios.

Performance: Path FX is literally like running SPICE on all of the clock trees for delay and variance, but in an STA environment with STA throughput. Path FX evaluated all of the clock trees in a 100 million instance, design in under three hours, front to back.

Production Proven Accuracy: FX has been validated at all of the major foundries, at 28nm, 20nm, 16nm, 14nm and 10nm, on all of the major models (BSIM4, BSIMSOI, PSP, BSIMCMG, etc.), and on multiple proprietary and all major third party libraries. It is currently in production at the most advanced process nodes on some of the leading SoC designs. FX results are typically within 2% of mean ±3σ of the leading commercial SPICE results.

Complete clock tree timing environment: Path FX is a complete clock tree timing environment. It reads standard data input formats; Verilog, SDC, SPEF, Liberty.

Clock Tree by Tree Reports: Path FX generates detailed reports by clock (insertion delay by end point/node along the tree, skew, histograms across the clock for transition times).

Easy integration into PrimeTime and PrimeTime SI: Path FX can directly find the clock trees from the design, or reads in a list of clock trees directly from PrimeTime or PrimeTime SI.

Calculates Corner or Statistical Timing: Path FX can calculate SPICE accurate timing from traditional sign-off corners, or statistically from global corners.

True Transistor Level Timing Captures True Circuit Timing:  FX is a transistor level model. This enables Path FX to inherently capture the real circuit level behavior. Waveforms are properly propagated through the gates, and receivers are treated as active loads (Miller effect).

Voltage Impact on Clocks can be modeled: Local voltage conditions (e.g. IR drop) can be directly annotated onto a clock tree at specific pins.  

Multi-Voltage Clock Support: Because FX is a transistor level model, Path FX is able to handle multi-voltage clocks automatically. Waveforms are correctly propagated through level shifters, and all voltages are properly resolved.

Voltage Sweeping and Multi-Corner Analysis:  Path FX also has the capabilities to perform multi-voltage clock sweeps (aka Shmoo plots), and multi-mode, multi-corner analysis.

 SDF Generation: Path FX supports the export of SDF files (standard delay format), which can be used to direct final sign-off timing or physical design optimization.

Easy Integration with Your STA and PD Flow

Path FX complements your existing sign-off and physical design flows. The inputs for the FX models are your libraries and foundry SPICE models. The inputs for Path FX are the design files (Verilog, SPEF, SDC), and, optionally, a list of critical clocks from your STA tool such as PrimeTime or PrimeTime SI. The outputs are timing reports, or SDF timing data that can be input back into your optimization tools or static timer.

Path FX: SPICE Accurate Timing Made Practical

Path FX has made SPICE accurate timing both possible and practical for SoC designs. It is fast, production proven at the most advanced process nodes, and functionally robust. It complements existing sign-off and physical design flows to materially improve chip frequency, yield and time to market.