The Miller Cap FinFET Menace!

The Miller Capacitance is a hidden timing killer in FinFETs. The Miller Capacitance can be the dominant parasitic capacitive effect in FinFET circuits – more than the wire load itself. Because existing STA tools and library models miss or understate the impact of the Miller Capacitance, this could result in yield and frequency problems in silicon.  

Properly accounting for the Miller Capacitance requires modeling the impact of an ‘active’ load both at the driver and the receiver, and propagating the real waveform that results through the rest of the path.

To learn more, we have created a white paper on Miller Capacitance. If you would not mind, we would like to know a little about you. We promise not to bother you, except for the annual "visit us at DAC spam blast." Please send us provide your name and work email address, and we will take you right to the link. Thanks!

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