The Miller Capacitance is a hidden timing killer in FinFETs. The Miller Capacitance can be the dominant parasitic capacitive effect in FinFET circuits – more than the wire load itself. Because existing STA tools and library models miss or understate the impact of the Miller Capacitance, this could result in yield and frequency problems in silicon.
Properly accounting for the Miller Capacitance requires modeling the impact of an ‘active’ load both at the driver and the receiver, and propagating the real waveform that results through the rest of the path.
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