Modeling Variation For Custom Logic Macros in FinFETs

 

One of the more interesting developments in FinFET SoC design is the return of custom logic and ‘macros’. These large functional blocks include large bit count register trays, pulse latches, retention flops, and programmatic delay buffers. In FinFETs, they can play an essential role in optimizing power, performance and area. These Macros require process variation models (AOCV, POCV, LVF) just like any standard cell. However, because these cells are very large, it is impossible to use MC SPICE. Macro FX is the first practical solution for variation modeling of custom logic.

To learn more, we have created a white paper on custom logic macros. Please provide us your name and where you work. We promise not to send you loads of unsolicited emails (though we may harass you briefly before DAC). The form will take you to the link. 

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