Isadore warns smaller process nodes cause Timing Sign-Off Deadlock

Jim Hogan got it right that digital design teams must manage systematic margining at multiple levels; including sources of variance, derates, and extensive cell characterization. However, when leading edge SOCs meet leading edge processes, systematic margining is only part of the challenge confronting sign-off timing.

This isn't about specific individual features in a Synopsys PrimeTime or Cadence Tempus -- it's about how you use them. To capture delay and slack calcs at 28 nm and below, most of the assumptions SoC teams used in the past are inadequate.

Designers must now also consider:

- What are the sign-off corners?

- What's the impact of frontend and backend of line variance?

- What additional electrical effects must now be considered?

Let's look at what's driving the re-examination of today's timing sign-off...

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