At smaller geometries modeling physical effects like process variation is an important part of a robust physical design flow. Today’s designs are required to operate within tight design specifications at multiple process, voltage, and temperature corners. It is important to consider these requirements in all phases of the design process.
The choice of margin strategy can affect timing closure and yield. Systematic margining of these sources of variability is important. Over margining costs design time and “quality of results” while under margining can risk the design or yield. This is especially important at 28nm and below.
Can we improve upon the state-of-the art by including additional factors in our margining strategy? For example, today both Advanced On-Chip-Variation (AOCV) and Parametric On-Chip-Variation (POCV) are commonly used in physical design flows to model the impact of process variation on cell delays. What is the benefit of adding variation effects? We know that process variation also affects cell transition times (slew), but these effects are often modeled with simplistic guard bands. We can do better.
This paper explains how AOCV derates and POCV coefficients are created. We demonstrate how to add extra factors like voltage variation using today’s derate methodology and design flows. The paper introduces the Liberty variance standard, and how it addresses the limitations of AOCV and POCV. Finally, we show the impact of choosing different margining strategies on a design and present how to assess the pros and cons of our choices in a systematic way.