Ahran and Joao win the TSMC "Customers' Choice Award" with Stage Based OCV paper from TSMC OIP 2011

Stage-based OCV derate tables are a systematic correction to liberty timing models to account for on chip process variation. Stage-based OCV can be used in timing and optimization tools as a fast approximation for statistical timing giving better – more accurate results and helping to close timing at smaller process nodes.

While stage-based OCV provides material improvements to timing margin over a fixed global OCV derate; worst case stage-based OCV derates can still be overly pessimistic – penalizing designs for variance outside their operating region. This paper explores the contributing factors to stage-based OCV pessimism and ways to improve the tables significantly. In addition, we demonstrate that different views of design specific derates that can be used for varying design purposes from timing to optimization 

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