Isadore Katz presented at DAC 2016 at a special session, "How Much Margin Do We Really Need?" We felt this was a 'timely' discussion, since almost every SoC team we meet with today asks "How do we recover margin?" The focus of our paper is how to use high accuracy timing to recover margin. What we have found is that every SoC team adds margin factors into static timing to account for all of the potential contributors that cannot be directly captured in the timing models. This margin stack has been steadily increasing with the shift into FinFETs, and makes timing closure extremely difficult. As importantly, the margin stack is driving power up as more and more buffers have to be added or upsized to account for the margin.
We believe that the best way to bring margin under control is to improve accuracy, and to get away from flat multipliers which are guaranteed to drive up power. Tools like Path FX, with their transistor level modeling, can dramatically reduce unnecessary negative slack, and put a spotlight on the paths that really need fixing.
To learn more about how to apply high accuracy timing methods to bring margin back under control, please download our presentation from DAC 2016.