Recovering Margin - The Evolution of Timing Sign Off DAC 2016

Isadore Katz presented at DAC 2016 at a special session, "How Much Margin Do We Really Need?" We felt this was a 'timely' discussion, since almost every SoC team we meet with today asks "How do we recover margin?" The focus of our paper is how to use high accuracy timing to recover margin. What we have found is that every SoC team adds margin factors into static timing to account for all of the potential contributors that cannot be directly captured in the timing models. This margin stack has been steadily increasing with the shift into FinFETs, and makes timing closure extremely difficult. As importantly, the margin stack is driving power up as more and more buffers have to be added or upsized to account for the margin. 

We believe that the best way to bring margin under control is to improve accuracy, and to get away from flat multipliers which are guaranteed to drive up power. Tools like Path FX, with their transistor level modeling, can dramatically reduce unnecessary negative slack, and put a spotlight on the paths that really need fixing. 

To learn more about how to apply high accuracy timing methods to bring margin back under control, please download our presentation from DAC 2016. 

Name *
Name

Path FX and Statistical Slack

With static timing, it all comes down to one thing – will each path pass or fail in production silicon? When paths fail, the chip either functions incorrectly (a hold violation) or clock speed must be reduced and/or power increased (set-up violation). These both have a direct impact on yield – the part fails to meet the product specification.

 

The ultimate static timing goal is MC SPICE accurate timing slack or statistical slack. Timing slack is the basic pass/fail test for STA, and it is the best way to measure margin.  The more slack that is recovered; the more margin that is recovered, and can be applied to power, timing closure, yield, area, etc

 

Path FX is the only commercially available, production proven, path based static timing solution that delivers MC SPICE accurate statistical timing and slack. Using transistor level timing, based upon the FX model, Path FX puts it all together to match MC SPICE: statistical arrival times, slews, and constraints, all correctly correlated, and combining to measure statistical slack. 

To learn more, we have created a white paper on statistical. Please provide us your name and where you work. We promise not to send you loads of unsolicited emails (though we may harass you briefly before DAC). The form will take you to the link.

Name *
Name

Path FX Gets Timing Right at Low Voltage - PT & Tempus Get it Wrong!

At very low voltage, 0.6V and below, circuit effects and variation break all of the estimations that PT and Tempus rely upon to calculate timing. Worst of all the corner values that everyone uses do not really tell you where the timing will end up. Just like analog designers use the MC SPICE to determine the average and the distribution for a circuit, path based timing needs to do the same thing. In fact, the difference between the average delay and the corner delay on a path at low voltage can be 10% or higher - bigger than the variance around the average itself. 

Path FX is the only solution that determines timing at low voltage accurately and efficiently. Because it is based on FX, a transistor level model, it is able to both find the true average delay just like MC SPICE, and take into account all of the circuit level effects that PT and Tempus struggle with (Miller Capacitance, nonlinear waveforms, slew variation, local voltage effects and IR drop...). 

At low voltage, Path FX is the answer. 

To learn more, we have created a white paper on low voltage timing. Please provide us your name and where you work. We promise not to send you loads of unsolicited emails (though we may harass you briefly before DAC). The form will take you to the link. 

Name *
Name


Modeling Variation For Custom Logic Macros in FinFETs

 

One of the more interesting developments in FinFET SoC design is the return of custom logic and ‘macros’. These large functional blocks include large bit count register trays, pulse latches, retention flops, and programmatic delay buffers. In FinFETs, they can play an essential role in optimizing power, performance and area. These Macros require process variation models (AOCV, POCV, LVF) just like any standard cell. However, because these cells are very large, it is impossible to use MC SPICE. Macro FX is the first practical solution for variation modeling of custom logic.

To learn more, we have created a white paper on custom logic macros. Please provide us your name and where you work. We promise not to send you loads of unsolicited emails (though we may harass you briefly before DAC). The form will take you to the link. 

Name *
Name

Process Variation, Timing Constraints and Ultra-Low Voltage

The corner timing constraints in your library today for lower voltages may be extremely optimistic due to process variation and hide timing violations. They are overstating the timing slack in the design.  You could be taping out with serious yield and power risks. Constraint uncertainty corrects corner based constraints for process variation and are an essential part of any advanced timing methodology. 

Please give us your email address, and company name, and we will take you to the article. 

Name *
Name

The Miller Cap FinFET Menace!

The Miller Capacitance is a hidden timing killer in FinFETs. The Miller Capacitance can be the dominant parasitic capacitive effect in FinFET circuits – more than the wire load itself. Because existing STA tools and library models miss or understate the impact of the Miller Capacitance, this could result in yield and frequency problems in silicon.  

Properly accounting for the Miller Capacitance requires modeling the impact of an ‘active’ load both at the driver and the receiver, and propagating the real waveform that results through the rest of the path.

To learn more, we have created a white paper on Miller Capacitance. If you would not mind, we would like to know a little about you. We promise not to bother you, except for the annual "visit us at DAC spam blast." Please send us provide your name and work email address, and we will take you right to the link. Thanks!

Name *
Name

A Brief Introduction to Liberty Variance Format

Liberty Variance Format is the most important innovation to the Liberty Timing Model since CCS. This paper provides an overview of LVF and how it can improve your timing sign-off and optimization flow. If you are considering FinFETs or ultra-low voltage operation, you should be considering LVF.

If you don't mind, we would like to know a little about you. Please send us provide your name and work email address, and we will take you right to the link. Thanks!

Name *
Name


Joao on a Framework for Responsible Timing at the TAU Workshop 2014

Joao discusses an industry customer framework that will enable timing sign-off at advanced process nodes from 20nm, 16nm, 14nm and beyond. 

Towards a Framework for “Responsible Timing”

Abstract—The purpose of this paper is to outline a new framework for sign-off timing flows for 20nm and below:  ‘Responsible Timing’. This framework defines the requirements from each of the key participants, foundry, EDA vendor and IC design house, criteria by which we can measure the flow effectiveness and a new approach to transparent, well articulated standards.

Read the conference paper by Dr. Joao Geada & Shiva Raja

View the workshop presentation

Isadore warns "Don't drink the SNPS/CDNS timing Kool-Aid!"

Hi John, I want to follow up with some "check to see if there is water in the pool before you dive in" warnings. There is a lot of confusion out there on:

- what are corners,

- the difference between traditional sign-off corners and global corners,

- how derates work, and

- how STA uses all of the above.

WARNING: Synopsys and Cadence are pushing new capabilities in derates and timing that are NOT compatible with existing sign-off practices -- and these derates are NOT blessed by TSMC, Samsung, nor GlobalFoundries. Before you sign up to Synopsys or Cadence derates for sign-off, it pays to learn what this all means.

http://www.deepchip.com/items/0535-01.html

Isadore warns smaller process nodes cause Timing Sign-Off Deadlock

Jim Hogan got it right that digital design teams must manage systematic margining at multiple levels; including sources of variance, derates, and extensive cell characterization. However, when leading edge SOCs meet leading edge processes, systematic margining is only part of the challenge confronting sign-off timing.

This isn't about specific individual features in a Synopsys PrimeTime or Cadence Tempus -- it's about how you use them. To capture delay and slack calcs at 28 nm and below, most of the assumptions SoC teams used in the past are inadequate.

Designers must now also consider:

- What are the sign-off corners?

- What's the impact of frontend and backend of line variance?

- What additional electrical effects must now be considered?

Let's look at what's driving the re-examination of today's timing sign-off...

http://www.deepchip.com/items/0534-03.html

Ahran at the 2013 ARM TechCon on Designing A Systematic Variance Methodology

At smaller geometries modeling physical effects like process variation is an important part of a robust physical design flow. Today’s designs are required to operate within tight design specifications at multiple process, voltage, and temperature corners. It is important to consider these requirements in all phases of the design process.

The choice of margin strategy can affect timing closure and yield. Systematic margining of these sources of variability is important. Over margining costs design time and “quality of results” while under margining can risk the design or yield. This is especially important at 28nm and below.

Can we improve upon the state-of-the art by including additional factors in our margining strategy? For example, today both Advanced On-Chip-Variation (AOCV) and Parametric On-Chip-Variation (POCV) are commonly used in physical design flows to model the impact of process variation on cell delays. What is the benefit of adding variation effects? We know that process variation also affects cell transition times (slew), but these effects are often modeled with simplistic guard bands. We can do better.

This paper explains how AOCV derates and POCV coefficients are created. We demonstrate how to add extra factors like voltage variation using today’s derate methodology and design flows. The paper introduces the Liberty variance standard, and how it addresses the limitations of AOCV and POCV. Finally, we show the impact of choosing different margining strategies on a design and present how to assess the pros and cons of our choices in a systematic way. 

Read the conference paper

View the presentation

Ahran on modeling Voltage Variation at TSMC OIP 2013

Ahran presents a detailed tutorial on how to model voltage variation as part of timing derates at the TSMC OIP Conference in 2013. For example, some design teams want to add margin for potential IR drop between the launch and capture portions of the clock. This tutorial addresses the different options for adding this margin along with process variation related timing derates. 

View the presentation

 

Ahran & Joao write about AOCV for EETimes

Applications and Use of Stage-based OCV

Stage-based OCV derate tables are a systematic correction to liberty timing models to account for on chip process variation. Stage-based OCV can be used in timing and optimization tools as a fast approximation for statistical timing giving better – more accurate results and helping to close timing at smaller process nodes. While stage-based OCV provides material improvements to timing margin over a fixed global OCV derate; worst case stage-based OCV derates can still be overly pessimistic – penalizing designs for variance outside their operating region. This paper explores the contributing factors to stage-based OCV pessimism and ways to improve the tables significantly.  In addition, we demonstrate that different views of design specific derates that can be used for varying design purposes from timing to optimization.

Read more...

 

Ahran and Joao win the TSMC "Customers' Choice Award" with Stage Based OCV paper from TSMC OIP 2011

Stage-based OCV derate tables are a systematic correction to liberty timing models to account for on chip process variation. Stage-based OCV can be used in timing and optimization tools as a fast approximation for statistical timing giving better – more accurate results and helping to close timing at smaller process nodes.

While stage-based OCV provides material improvements to timing margin over a fixed global OCV derate; worst case stage-based OCV derates can still be overly pessimistic – penalizing designs for variance outside their operating region. This paper explores the contributing factors to stage-based OCV pessimism and ways to improve the tables significantly. In addition, we demonstrate that different views of design specific derates that can be used for varying design purposes from timing to optimization 

Read the paper