SPICE Accurate Statistical Timing for 40nm and Below

Amber Path FX, with 40nm libraries from TSMC, is an accurate, fast, and practical solution for high accuracy timing of nanometer designs. Amber Path FX uses transistor level statistical static timing analysis (TSSTA) to achieve near SPICE accuracy for both delay and variance.

Fast!

Amber Path FX is 100,000x faster than Monte Carlo SPICE. With its multi-threaded simulator, Amber Path FX can evaluate thousands of paths per processor per hour (vs. days per path in SPICE).

Accurate

Amber Path FX uses Transistor Statistical Static Timing Analysis (TSSTA) to achieve near SPICE accuracy for both delay and variance. Amber Path FX was developed in partnership with TSMC, and libraries are based directly on TSMC's 40nm SPICE model. Libraries can be characterized in hours vs. weeks for CCS or ECSM libraries.

Practical

Amber Path FX works directly with PrimeTime™ and PrimeTime-SI™. It fits directly into existing design flows and automatically imports a list of failing paths from any PT or PT SI run, and analyzes them for delay and variance. Amber Path FX SSTA also imports SI delays from PT SI or Celtic and includes them in its calculation of path delay.

Free 30 day trial

Amber Path FX is available for a free 30 day trial. Request a copy today.

Why use Amber Path FX

Traditional timing tools waste up to 20% of the timing margin in a 40nm design. SPICE and Fast SPICE Monte Carlo solutions provide the accuracy needed for sign-off, but they lack the performance to address even a small fraction of the critical paths in a design. Much of the value of today's advanced processes is effectively left on the table.

In 40 Nanometer and Below, Every Design Requires Accuracy

In 40 Nanometer and below, every bit of design margin has to be used. Whether it is power, yield, clock frequency, or simply just signing-off for tape-out, design closure is getting harder, not easier. This is partly due to the ongoing specification race; e.g. 1 GHz low power mobile processor designs. But it is also due to the fact that manufacturing variance in small geometries appears to be eroding the traditional power/performance gains that were automatically expected from new semiconductor process generations.

However, this erosion is not "real." Much of it comes from the artificial pessimism created by traditional sign-off methods that rely on manufacturing corners, and deliberate addition of "padding" for protection. In 40nm, this pessimism means that after dozens of P&R and optimization iterations, designers typically find 1000's of paths which are "failing" according to traditional STA tools and corner based methodologies.

Until now, the only accurate alternative that could find the margin and eliminate the pessimism was Monte Carlo SPICE. However, checking one timing violation with Monte Carlo SPICE literally takes days - not a viable alternative with 1,000s of violations.