Amber is an integrated suite of static analysis tools for high-performance, cell-based designs. Amber is being used in production on some of the largest and most advanced circuits in design today, ranging from 10m to well over 40m instances. Users can analyze bigger circuits faster and more completely, and then isolate problems to make trade-offs and trial solutions in a fraction of the time it takes today.

Amber STA delivers 4x to 8x throughput improvement over current static timing tools with the ability to consider multiple factors or corners simultaneously.

Amber SI extends Amber's capabilities with signal integrity analysis.

Amber Path FX is a path based statistical timing analyzer that enables users to analyze both delay and variance within 2% of SPICE.

Fast transistor models (FXM) provide near SPICE accuracy for standard and variance aware timing analysis. FXM libraries are also the basis for transistor level statistical static timing analysis (TSSTA) – available in all of the Amber products.

The Amber API provides pivotal capabilities for next generation tools and flows. Amber API provides complete programmable access to all of the Amber capabilities. It is the first and only commercially available API that enables threaded and incremental timing and signal integrity analysis.  It is designed to be embedded in to existing software and replaces cumbersome file processing or scripted integration with a timing tool.

All of the Amber products are based on an industry leading Amber timing platform. Built from the ground up with today's modern CPU architectures in mind - performance scales linearly with the number of CPUs.

Amber addresses known limitations in the current static analysis flow.

• Speed: 4x or more faster than current tools for timing and signal integrity. The first tool to support threaded static analysis, including signal integrity. Performance scales linearly with the number of CPUs.
• Capacity: Amber uses dynamic memory scaling to facilitate full chip timing of the largest circuits in design today. 10m instance designs can be analyzed in less than 10GB, while 40m instance designs can be analyzed in under 32GB.
• Accurate Incremental: 100x more throughput with accurate incremental capability. Allows users to make complex circuit changes from block level hierarchy, to cell swap-outs, to logic changes, and then incrementally calculate timing and signal integrity results. Most importantly, it gives exactly the same answer as if the entire design had been re-run. Conventional tools claim incremental capability but provide incorrect results and radically limit the type of circuit changes that can be made.
• SI Pessimism Reduction eliminates overly pessimistic cases in signal integrity analysis without compromising the safeness of the answer through use of multiple heuristics. The fast transistor model (FXM) delivers near SPICE accuracy with fully threaded performance.
• Statistical: TSSTA delivers transistor accuracy for delay and variance. Characterization of FXM libraries is done in hours, not days or weeks.
• SI Pessimism Reduction: Eliminates overly pessimistic cases in signal integrity analysis without compromising the safeness of the answer through use of multiple heuristics.
• Analysis and Debug: New features enable debug and isolation of timing problems. These include design of experiments, what-if and what’s next analysis, multi-corner/mode/experiment analysis, diagnostics, and statistical views.  All data is saved automatically and can be analyzed later with little to no overhead.