In The News.....
CLK Design Automation
in TSMC 10.0 Reference Flow
SAN FRANCISCO—Leading chip foundry Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) Wednesday (July 22) introduced its latest design reference flow, said to extend the company's recommended design methodology to the 28-nanometer (nm) node.
TSMC's Reference Flow 10.0 addresses new design challenges at 28-nm and includes innovations to enable system-in-package (SiP) design, according to TSMC (Hsinchu, Taiwan).
New to the flow is an RTL-to-GDSII chip implementation track from Mentor Graphics Corp., TSMC said. Other EDA partners in the flow include Synopsys Inc., Cadence Design Systems Inc. and Magma Design Automation Inc., TSMC said, as well as Altos, Anova, Apache, Azuro, CLK DA, Extreme DA, and Nannor.
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