Press Releases
- CLK Design Automation Awarded TSMC's OIP Customers' Choice Award
- CSR Selects CLK Design Automation’s AOCV FX
- CLK DA Announces Design Specific Stage-based OCV and Constraint Uncertainty for TSMC Reference Flow 12
- CLK Design Automation announces High Accuracy Signal Integrity Timing Analysis
- Matthew Raggett Joins CLK Design Automation as Vice President of Field Operations and Business Development
- CLK Design Automation Announces Design Specific AOCV Table Generation
- CLK Design Automation Announces Breakthrough Acceleration for AOCV Table Generation
- CLK Design Automation Awarded U.S. Patent 7793243 for Multi-Engine Static Analysis
- CLK Design Automation Delivers High Accuracy Timing and Stage Based OCV Table Characterization for TSMC Reference Flow 11.0
- New TSSTA Solution is 100,000x Faster Than Monte Carlo SPICE
TSMC Reference Flow Announcements
Reference Flow 12
Reference Flow 11
CLK Design Automation Inc today announced that it has delivered a range of high accuracy timing solutions for TSMC Reference Flow 11.0, and as part of TSMC’s 40nm solution. Amber Path FX™ has been validated by TSMC for SBOCV Table Characterization. Amber Path FX™ has also met TSMC’s requirement as a Fast SPICE accurate timing and variance analysis for TSMC’s 40nm high performance (G) and low-power (LP) technologies.
Reference Flow 10
EETimes.com / SAN FRANCISCO—Leading chip foundry Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) Wednesday (July 22) introduced its latest design reference flow, said to extend the company’s recommended design methodology to the 28-nanometer (nm) node.
Reference Flow 9
EDN / Statistical static timing analysis (SSTA)—theory, thesis project, IBM proprietary technology—is about to add one more stage to its evolution: mainstream member of the design flow
