Category Archives: Variance

CLKDA’s AOCV FX Makes DeepChip’s Top 5 Tools shown at DAC ‘13

Littleton, MA, October 31, 2013 – CLK Design Automation today announced that AOCV FX™ timing derate generator was voted one of top 5 hot tools shown at the Design Automation Conference (DAC) in DeepChip’s annual user survey. DAC is the electronic design automation (EDA) industry’s premier conference, and users reviewed the products exhibited there.

“I give a big congrats to CLKDA’s products ranking in the top 5 with chip designers at DAC,” said John Cooley, DeepChip’s moderator. “AOCV helps customers in trouble. Getting to sign-off keeps getting harder, and designers specifically commented on how fast CLKDA generated instance-specific derates.”

To see the user feedback, visit:

Read the full press release here…


Liberty Technical Advisory Board Announces Membership Grows to 16

“Liberty is the cornerstone for library models and we are delighted to become part of the Technical Advisory Board,” said Isadore Katz, President and CEO of CLK Design Automation. “We look forward to working with the LTAB to extend Liberty with robust derate and variance formats. We believe this will be invaluable to the designers who are making commitments to 20nm, 14nm and beyond.”

Read the full press release here…


CLK Design Automation, Inc. Joins Liberty TAB

LITTLETON, Mass., Dec. 17, 2012 /PRNewswire/ — CLK Design Automation today announced that it has joined the Liberty Technical Advisory Board. Timing derates for process variance, temperature and voltage have become an essential part of 28nm, 20nm and 14nm physical design flows. Today, timing derates depend on a number of different formats including AOCV, OCV and proprietary extensions. CLK’s goal is to help in the standardization of timing derates and variance models based upon the Liberty™ library format, the de facto standard for integrated circuit (IC) and signoff.

“Creating a robust standard for variance models and timing derates will be critical for broad adoption of advanced semiconductor process nodes,” said Isadore Katz , President and CEO of CLK Design Automation, Inc. “It will enable EDA tool vendors, IP suppliers and Semiconductor Foundries to address the challenges of achieving good manufacturing yields with today’s aggressive chip design specifications for power, performance and high levels of system integration.”

“The LTAB welcomes participation from CLK-DA,” said Jim Sproch , LTAB chair.  “CLK-DA brings new ideas and an additional perspective on OCV and we look forward to their involvement in aligning the industry on consistent ways of thinking about and modeling OCV.”

Timing Derates

Timing derates help designers model process variance, temperature, and voltage during the physical design and timing sign-off process. These derates combine manufacturing process information along with other factors, some environmental, some design or library specific, into a set of values that adjust the calculated timing delays to ensure high manufacturing yield.

Today’s leading edge methodologies use AOCV or Advance On Chip Variation. Advanced stage-based on chip variation is a substantial improvement in modeling process variation compared with traditional methods. It can improve design performance and identify complex bugs that might have been masked with traditional timing methods. However, building complete, accurate AOCV tables for full libraries calls for millions of SPICE Monte Carlo runs, which is simply impractical even with unlimited compute resources and software licenses. Moreover, basic methods for generating SBOCV tables are unnecessarily pessimistic. Because they rely on the worst case load and slew they do not reflect the way cells are actually used in a design, and may misdirect the optimization flow.

AOCV FX from CLK Design Automation: Advance Timing Derates Made Practical

AOCV FX is the first practical, turn-key solution that has the performance and accuracy needed to generate a full database of SBOCV derate factors. Derate tables created by AOCV FX can be used with all of the leading timing and optimization tools.  AOCV FX can help designers correct for unnecessary process pessimism, and incorporate other margin factors for voltage, temperature, and delay accuracy.

About CLK Design Automation

CLK Design Automation is the leader in high accuracy timing variation solutions for nanometer semiconductor designs. CLK DA was founded in 2004, and is backed by Morgenthaler Venture Partners and Atlas Ventures. Path FX and AOCV FX are fast, accurate, and practical solutions for timing closure.

Amber, Path FX, and AOCV FX are trademarks of CLK Design Automation. All other trademarks or registered trademarks are the property of their respective owners.

Ahran Dunsmoor
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ICCAD workshop on Variability Modeling

We’ll present a poster at the IEEE Workshop on Variability Modeling and Characterization at ICCAD on Thursday.

Shiva Raja will be there to show how our FX transistor model and simulation engine can be used to reduce corners in traditional static timing analysis (STA). The paper also shows that setup and hold constraints are not correctly predicted by corner models while statistical FX models provide more accurate results.

CLK DA Announces Design Specific Stage-based OCV and Constraint Uncertainty for TSMC Reference Flow 12

Littleton, MA, June 1 – CLK Design Automation today announced support for TSMC’s Reference Flow 12.   CLK DA extended its leadership in high accuracy timing solutions with design specific stage-based OCV (SBOCV) table generation and added support for timing constraint uncertainty table generation. Both of these capabilities can be used with any STA or optimization solution that supports stage-based OCV  or constraint uncertainty for TSMC Reference Flow 12.0.
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Fast AOCV Table Generation

We’ve improved our AOCV table generator a lot over the past year. Compared to this time last year our table generator is about 500 times faster. That’s a million times faster than Monte Carlo SPICE.  Where you might spend a week or a month getting tables made for a handful of cells with a commercial SPICE you can now spend a day or two building AOCV tables for a full library with Amber Path FX.

We support threaded operation for machines with many processors or distributed operation for server farms or cloud based table generation.  The speed up is linear as CPUs or machines are added.

With the introduction of our AOCV database you can build a database of AOCV table values and then generate tables over and over again in less than a minute each.  This will let you experiment with different criteria for building tables or to create special purpose tables for whatever you are doing at the moment. The database has all the information needed to build tables for any load/slew combination for each cell.



Data Driven Development – Part 2

Generating SBOCV/AOCV derate tables for a cell involves calculating a derate value for a number of load/slew combinations.

In the graph below we’ve calculated the derate for 4 cells at various load/slew points. The colors are darkest approaching 1 and brighter as the derate value moves away from 1. The + symbols show the library’s load/slew points.


Besides being fast, the latest version of Amber Path FX supports saving all derate calculations and results to a database.  You can now change the load/slew selection criteria and generate new derate tables in seconds.  We are adding the ability to mine this data and perform variance checks to ensure your design is operating as you expect. We are just now learning how useful this information might be – not only to improve timing results but also to make optimization choices.

The other thing that these graphs show is how unsafe using a few cherry-picked load/slew points can be.  That’s the methodology some have suggested in order to make generating AOCV tables more palatable with other SPICE tools.

With Amber Path FX you don’t have to make those choices up front. You can generate an SBOCV database with a large range of load/slew points (the full set from the library or based on your design rules) and then refine based on how the cells are actually used.

We’ll have a lot more to say about this at the TSMC Technology Symposium in a few weeks but if you have questions now feel free to get in touch.


Data Driven Development

We’ve been taking a very close look at the data going in to and out of our software.  Some times the data validates our original assumptions. Other times the data takes us in new and interesting directions.  Here’s a picture that we found very enlightening


I’ll explain what this is in another post but here is a hint. It has to do with our work with SBOCV/AOCV.

SBOCV / AOCV Table Generation now 2x faster

Last fall I mentioned that we made performance improvements to AOCV table generation.  At the time we sped up the simulation for complex cells and added the ability to distribute the characterization across multiple machines.

In the last month we’ve improved the performance again – getting a 2x boost across the board regardless of whether the work is on a single machine or distributed on your server farm.  We’ve got another 30% improvement in the short term pipeline and more ideas that we’ve just started looking at in detail.  With more and more back end tools adding AOCV support we are excited to be able to help design teams create tables faster than ever before.