Some times big performance breakthroughs require taking a step back and reexamining a problem. We’ve done just that for SBOCV table generation and are really pleased with the outcome. (Stage based on chip variation is also sometimes called AOCV.) We can now generate tables for all the combinatorial cells in TSMC 40LP library in just [...]
Archive by Author
System Level Design for Variability
Ed Sperling at the SLD blog wrote an interesting article a while ago on the challenges facing designers at 32 and 28 nm. In the article he lamented that the big EDA companies are leaving their customers to do the hard work of designing with variability in mind. He is right that the big EDA [...]
report_timing -with_spice_accuracy -and_statistical -fast
Wouldn’t it be nice if your static timing tool had the ability to give you results with the accuracy of SPICE, handled variation, and still ran really fast? We’ve just introduced something that does just that. Amber Path FX is a new take on statistical STA. It’s the first practical tool for getting SPICE accurate [...]
Welcome to 40nm and Below
Digital engineers working in the world of 40nm and below are focused on quality and productivity like never before, but truth be told there’s more to be done. Because of the inherent process variation in 40nm, designers are sacrificing performance, area and power. Traditional corner based static timing methods are too conservative, and existing statistical [...]
Follow @clkda on Twitter