CLK Design Automation is the technology leader in timing and performance closure for nanometer semiconductor designs. Amber, our solution for timing, signal integrity and power is 4x - 8x faster than Synopsys PrimeTime. Amber FX SSTA is part of the TSMC 10.0 Reference Flow.  ClkWorks, our optimization solution, delivers timing and power closure for the most complex designs.

CLK DA received funding from Morgenthaler Venture Partners and Atlas Ventures. Its Board of Directors includes Axel Bichara and Karim Faris from Atlas, Bob Pavey and Paul Levine from Morgenthaler, and noted EDA entrepreneur and visionary Jim Hogan

“In 65 Nanometer and Below, All Paths Become Critical”

Timing and performance closure are major nanometer design obstacles, particularly for high speed (processors) and low power (mobile) designs. With designs reaching 100m place-able instances (400m+ gates), each optimization and timing analysis pass can take days.

In nanometer designs, every path becomes “critical.” All the speed paths must be boosted until they hit the target spec. Every other path must be optimized for power so that it is just on the edge of becoming a critical speed path. And because nanometer designs are so sensitive to electromagnetic effects, the most time-consuming calculation has to be used to verify performance - full signal integrity.

On top of all this, designers are struggling to deal with nanometer manufacturing variance. It is not uncommon to find teams running 32 or more process and metal timing corners, and then have to run multiple operating modes against those corners. The combination of modes and corners can result in 100 or more distinct timing evaluations. While statistical timing has been proposed as an alternative to corners, the reality of these tools is that they are painfully slow, and require specialized libraries that can take weeks to create.

The resulting trade-offs between dynamic power, leakage and speed have become extremely complicated. Designs go through dozens of iterations to achieve performance specifications against all possible operational conditions and manufacturing corners.

There is intense dissatisfaction with the current timing and optimization solutions at leading users. Users consistently complain about their timing tools: from long run times, to poor debug and reporting capabilities, and then to the poor optimization results.

Amber: Timing Analysis Tool Suite and Platform

Amber was specifically designed for nanometer design analysis, both as a tool suite for end users, and as a platform for application development and flow integration. Amber combines break through performance (4x to 8x faster than PrimeTime), and major functionality improvements. Amber enables users to analyze bigger circuits, faster, and more completely, and then to isolate problems, make trade-offs and trial solutions in a fraction of the time it takes today. Its patent-pending threaded and incremental architecture ensures that Amber can address these design challenges over the next decade.

As a timing and power analysis tool suite, Amber delivers 4x to 8x throughput improvement over current tools with the ability to consider multiple factors or corners simultaneously (timing, leakage, statistical variance, signal integrity and transistor), and advanced analysis and debug capabilities. Amber is drop-in compatible with existing scripts, and delivers the same static timing results as PrimeTime®.

As a platform, Amber provides pivotal capabilities for next generation tools and flows. It is the first and only commercially available tool that enables threaded and incremental signal integrity analysis. Performance scales linearly with the number of CPUs. It is fully modular; enabling us to easily add and improve our algorithms. Moreover, Amber has a complete API (which we use internally) to facilitate easy integration into other tools and flows.  This positions Amber to be at the heart of any next generation EDA tool flow.

ClkWorks: Clock Driven Optimization

ClkWorks was designed for the planning, implementation and optimization of high performance and low power ICs.  ClkWorks includes three major components:  Topological Routing for variance tolerant clock trees, Hybrid CTS for low power, high speed clocks, and Sign-OFf Driven Optimization for reduction of power and negative slack after placement or routing.

ClkWorks uniquely uses the clock as a central leverage point to improve timing, reduce power, and increase tolerance to process variance. ClkWorks can be used in conjunction with existing clock tree synthesis and clocking implementation tools, or as an alternative mechanism for clock implementation.

Sign-Off Driven Optimization

ClkWorks uniquely calls on sign-off timing during the optimization phase to make sure that its results truly improve power and negative slack.  In place and route tools, where timing can be off by 100 to 100 ps on 1 ns clock, optimization is just as likely to make a circuit worse as better.  ClkWorks optimization works with either Amber or PrimeTime® to ensure that its results are sign-off quality .