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CLKWorks Clock Design Suite

CLKWorks is an integrated suite of tools for variance-tolerant clock tree synthesis and optimization. ClkWork’s innovative intelligent clock scheduling technology enables radical improvements in power consumption, timing closure and on chip variance tolerance. CLKWorks is being used in production on some of the largest and most advanced circuits in design today.

CLKWorks has three major components: Topology Planner, Clock Tree Synthesis, and Optimizer. Together, they create a unique hybrid clock design solution that delivers significant improvements in variance tolerance, insertion delay, power and skew. Each of these components can also be used independently with existing clocking and physical design tools.

Clock design is one of the key bottlenecks in today’s IC design flows. The combination of 10-million plus instance circuits with nanometer process variation makes it very difficult to implement a clock that satisfies performance and power targets. Mesh based methods consume too much power or require packages that are too expensive for many applications. Traditional clock tree synthesis (CTS) approaches, are extremely sensitive to process and metal variation. Moreover, traditional   CTS methods force tight synchronization between paths that are completely independent. Too many buffers get inserted, dynamic power increases, and clock routing can be torturous. These over-constrained clocks in turn make timing closure very difficult by effectively taking the margin out of the circuit.

CLKWorks addresses known limitations in the current clock tree synthesis flow:

• Manufacturing Variance Tolerant Clocking: By combining symmetrically balanced routing for the top levels of the clock, with intelligent clustering for CTS, CLKWorks generates clocks that are effectively immune to device and metal variance.
• Significant Reductions in Power: CLKWorks materially reduces the number of buffers required. In multiple 65nm and 45nm test cases, CLKWorks reduced total buffer count by 20% or more compared with mainstream CTS solutions.
• Better Insertion Delay and Skew: CLKWorks hybrid CTS approach consistently delivers materially lower insertion delay, and skew than mainstream CTS solutions.
• Multi-corner/multi-mode: CLKWorks is inherently multi-corner, multi-mode. Whether it is used for full CTS, or for post-CTS optimization, CLKWorks simultaneously evaluates and satisfies all timing corners and scenarios.
• Significant Improvements in Timing Closure: By using intelligent clock scheduling (ICS) based on local synchronization, CLKWorks Optimizer has demonstrated 20% or more reductions in total negative slack and worst negative slack both pre and post routing. It also improves immunity to IR drop by reducing simultaneous register switching.
• Support for Advanced Clock Topologies: CLKWorks supports clock gating, multiple clock domains, and multiple voltages.

The CLKWorks Clock Design Suite has three major components.

1. Clock Planner: The Clock Planner is built around a topologically symmetrical router, and is used for the top level of the clock tree. It matches manually routed solutions in QOR and automates several weeks of work in less than an hour. It creates logical and physical symmetry on the clock network. There is exact symmetry in wire-length and buffer levels to each sink. Every level of the clock network is symmetrical with adjacent branches in wire length and metal composition. Multiple routing scenarios are generated with user control on routing layers & branching depth. It concurrently does topology generation, buffer insertion, sizing and routing. It works at the top-level, block level or on flat designs and has support for channel and over-the-block routing methods. It matches detailed routing and extraction delays within 2% of industry standard extractors.
2. Clock Tree Synthesis: CLKWorks CTS supports traditional clock tree generation  with support for multiple clock domains, voltage domains, clock gating, and cloning. It leverages the Optimizer to reduce total buffer count, minimize insertion delay, skew, and simultaneous switching. CLKWorks CTS also supports a unique hybrid CTS when combined with the Clock Planner. Within a block, CTS will automatically determine the best partitioning of the design into clocking clusters. The upper levels of the block will be routed symmetrically, while the lower clusters will use CTS to minimize local skew.
3. Optimizer:  The CLKWorks Optimizer can be used pre- or post-routing to optimize clock trees for buffer count, skew, worst negative slack, and total negative slack. It is inherently multi-mode, multi-corner. The Optimizer is based on intelligent clock scheduling.  ICS enables a clocking methodology known as Local Synchronization: registers that feed each other should be tightly synchronized together. Conversely, if two parts of the design do not share any dataflow, then skew is permitted, even if they share the same clock. ICS brings multiple factors into a single algorithmic framework. ICS considers the timing constraints, physical topology of the placement, data flow between the registers, and numerically determines the ‘permissible skew range’ for every register to register path. Permissible skew is essentially a single figure of merit, a timing window between setup and hold, which takes into account all of the signals arriving into a register and all of the signals leaving the register. 

For additional information, please contact: sales@clkda.com, 978.486.1056 ext. 201

CLK Design Automation, Inc.

295 Foster Street

Littleton, MA 01451

www.clkda.com

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